Home | Login | Register Now [Mar 11,2010]

For Registered Users

Achieve 533MHz FPGA memory data rates
Author: Paul Evans

This article examines the architecture behind the I/O blocks in high-end FPGAs and how these FPGAs are able to achieve 533MHz or 1,067Mbit/s data rates.

Please login or register with us to view this article>>

Not a registered user?

Email address:
Password:
Confirm password:
User name :	First name Last name
Company name:
Mobile number:
Job function:
Products/Services:
Country/Area:	India Other Country/Area

Already registered? Login to view complete content.

Email address:
Password:
	Password is case-sensitive.
	Remember password Forgot your password?

	If you have already registered on the following websites, please log in using your email address and password
EE Times-India sites: EE Times-India EE Times-Asia EE Times-Taiwan EE Times-Korea EE Times-China Analog/Mix signal Power Systems Power Design India Home Entertainment Handheld Device Industrial Controls Auto Electronics

If you have already registered on the following websites, please log in using your email address and password

EE Times-India sites:

	Latest News
Transitioning from ADXL202 to ADXL213 or ADXL203 (11/03/10)

Go to top

eMedia Asia	EE Times - India\|Power Design India\|EE Times - Asia\|\|\|\|IIC-China
Global Sources	\|\|\|Electronic Components\|Computer Products\|Trade Show Center
TechInsights	EE Times\|ESM Online

Copyright © 2010 eMedia Asia Ltd. All rights reserved. Reproduction in whole or in part in any form or medium without the express written permission of eMedia Asia Ltd. is prohibited. Warning: The images on this site are protected by digital watermark technology. Your use of this website is subject to, and constitutes acknowledgement and acceptance of our Terms of Use.