Home | Login | Register Now [Jul 30,2010]

For Registered Users

The partitioning challenge of ASIC design into multiple FPGAs
Author: Juergen Jaeger

Partitioning a large ASIC design into multiple FPGAs can be challenging. Doing some upfront planning and selecting the right tool flow can make achieve a thoroughly verified ASIC and first-silicon success.

Please login or register with us to view this article>>

Not a registered user?

Already registered? Login to view complete content.

Email address:
Password:
	Password is case-sensitive.
	Remember password Forgot your password?

	If you have already registered on the following websites, please log in using your email address and password
EE Times-India sites: EE Times-India EE Times-Asia EE Times-Taiwan EE Times-Korea EE Times-China Analog/Mix signal Power Systems Power Design India Home Entertainment Handheld Device Industrial Controls Auto Electronics

If you have already registered on the following websites, please log in using your email address and password

EE Times-India sites:

	Latest News
ECG implementation on the TMS320C5515 DSP medical development kit (30/07/10)

Go to top

eMedia Asia	EE Times - India\|Power Design India\|EE Times - Asia\|\|\|\|IIC-China
Global Sources	\|\|\|Electronic Components\|Computer Products\|Trade Show Center
TechInsights	EE Times\|ESM Online

Copyright © 2010 eMedia Asia Ltd. All rights reserved. Reproduction in whole or in part in any form or medium without the express written permission of eMedia Asia Ltd. is prohibited. Warning: The images on this site are protected by digital watermark technology. Your use of this website is subject to, and constitutes acknowledgement and acceptance of our Terms of Use.